A pipeline ADC (analog to digital converter) is generally preferred to achieve a speed of 100 MSPS (mega samples per second) in high speed applications. However in recent years, with the advent of UDSM (ultra deep sub micron) technologies and improved capacitor matching techniques, successive approximation register analog to digital converter (SAR ADC) is a fast emerging alternative to the pipeline ADCs. The fact that pipelined ADCs require active amplifiers which comes at the cost of high power makes SAR ADCs a good architectural choice as its static power requirement is limited to a zero crossing detector which consumes a low power.
In an N-bit SAR ADC, the analog to digital conversion is done serially and hence requires N steps. Thus, a SAR ADC seeking to produce a 10 bit output has to perform 10 bit trials. Therefore, the SAR ADCs are inherently slow. In high speed applications, for example application at 100 MSPS throughput with 10 bit resolution, the SAR ADC is required to operate at 1 GHz. However, the SAR ADC has inherent problems. These problems include capacitive loading and charge kick back. The capacitive loading is caused by parasitic capacitances. The parasitic capacitances are created by switches and capacitors used in the SAR ADC. The charge kick back is caused by capacitors in the SAR ADC. An input driver provides an input voltage to the SAR ADC. The capacitors kick back a non-linear charge into the input driver, and this non-linear charge is required to be settled in a sampling time of the input voltage.